TinyTPU: SystemVerilog Systolic Array Compiled to WASM, Running Live in Browser

Core summary

One sentence to understand this update

TinyTPU is a 4x4 weight-stationary systolic array implemented in SystemVerilog, compiled to WASM, and running live in the browser, with its RTL verified against numpy.

Impact & opportunity

What this could mean

Chip design and AI inference optimization developers can draw inspiration from TinyTPU to explore the potential of deploying efficient AI hardware acceleration in web environments.